integrated device technology, inc. the idt logo is a registered trademark of integrated device technology, inc. functional block diagram fast cmos 16-bit bus transceiver/ registers (3-state) idt54/74fct16646t/at/ct/et idt54/74fct162646t/at/ct/et 1 b 1 1 a 1 1 oe 1 dir 1 sba 1 sab 1 clkba 1 clkab 2540 drw 01 to 7 other channels b reg a reg d c c d 2 a 1 2 oe 2 dir 2 sba 2 sab 2 b 1 2 clkba 2 clkab 2540 drw 02 to 7 other channels b reg a reg d c c d 74fct162646t/at/ct/et 16-bit registered transceivers are built using advanced dual metal cmos technology. these high-speed, low-power devices are organized as two inde- pendent 8-bit bus transceivers with 3-state d-type registers. the control circuitry is organized for multiplexed transmission of data between a bus and b bus either directly or from the internal storage registers. each 8-bit transceiver/register fea- tures direction control (xdir), over-riding output enable con- trol (x oe ) and select lines (xsab and xsba) to select either real-time data or stored data. separate clock inputs are provided for a and b port registers. data on the a or b data bus, or both, can be stored in the internal registers by the low-to-high transitions at the appropriate clock pins. flow- through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. the idt54/74fct16646t/at/ct/et are ideally suited for driving high-capacitance loads and low-impedance backplanes. the output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. the idt54/74fct162646t/at/ct/et have balanced output drive with current limiting resistors. this offers low ground bounce, minimal undershoot, and controlled output fall timesCreducing the need for external series terminating resistors. the idt54/74fct162646t/at/ct/et are plug-in replacements for the idt54/74fct16646t/at/ct/et and 54/74abt16646 for on-board bus interface applications. military and commercial temperature ranges august 1996 1996 integrated device technology, inc. 5.13 dsc-4231/9 1 description: the idt54/74fct16646t/at/ct/et and idt54/ features: common features: C 0.5 micron cmos technology high-speed, low-power cmos replacement for abt functions C typical t sk (o) (output skew) < 250ps low input and output leakage 1 m a (max.) C esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) C packages include 25 mil pitch ssop, 19.6 mil pitch tssop, 15.7 mil pitch tvsop and 25 mil pitch cerpack C extended commercial range of -40 c to +85 c Cv cc = 5v 10% features for fct16646t/at/ct/et: C high drive outputs (-32ma i oh , 64ma i ol ) C power off disable outputs permit live insertion C typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25 c features for fct162646t/at/ct/et: C balanced output drivers: 24ma (commercial), 16ma (military) C reduced system switching noise C typical v olp (output ground bounce) < 0.6v at v cc = 5v,t a = 25 c
5.13 2 idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges pin configurations 1dir 1 clkab 1 sab gnd 1 a 1 1 a 2 v cc 1 a 3 1 a 4 gnd 1 a 5 1 a 6 1 a 7 1 a 8 gnd 2 a 1 2 a 2 v cc 2 a 3 2 sab 2 a 5 2 a 4 2 a 7 gnd 2 a 8 2 clkab 2 dir 2 a 6 1 b 1 1 b 2 gnd 1 b 3 1 b 4 v cc 1 b 5 1 b 6 1 sba 1 b 7 1 b 8 2 b 1 2 b 2 gnd 2 b 3 2 b 4 v cc 2 b 5 gnd 1 clkba 2 b 7 2 b 6 2 b 8 gnd 2 sba 2 clkba 1 oe 2 oe 47 37 38 39 40 41 42 43 44 45 46 33 34 35 36 56 55 49 50 51 52 53 54 48 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 29 30 31 32 25 26 27 28 2540 drw 04 cerpack top view e56-1 1 b 1 1 b 2 gnd 1 b 3 1 b 4 v cc 1 b 5 1 b 6 1 oe 1 sba 1 b 7 1 b 8 2 b 1 2 b 2 gnd 2 b 3 2 b 4 v cc 2 b 5 gnd 1 clkba 2 b 7 2 b 6 2 b 8 gnd 2 sba 2 clkba 2 oe 1dir 1 clkab 1 sab gnd 1 a 1 1 a 2 v cc 1 a 3 1 a 4 gnd 1 a 5 1 a 6 1 a 7 1 a 8 gnd 2 a 1 2 a 2 v cc 2 a 3 2 sab 2 a 5 2 a 4 2 a 7 gnd 2 a 8 2 clkab 2 dir 2 a 6 2540 drw 03 47 37 38 39 40 41 42 43 44 45 46 33 34 35 36 56 55 49 50 51 52 53 54 48 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 ssop/ tssop/tvsop top view so56-1 so56-2 so56-3 29 30 31 32 25 26 27 28
idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges 5.13 3 pin description function table (2) capacitance (t a = +25 c, f = 1.0mhz) 2540 tbl 01 note: 1. this parameter is measured at characterization but not tested. 2540 tbl 02 notes: 2540 tbl 03 1. the data output functions may be enabled or disabled by various signals at the x oe or xdir inputs. data input functions are always enabled, i.e. data at the bus pins will be stored on every low-to-high transition on the clock inputs. 2. h = high voltage level l = low voltage level x = don't care - = low-to-high transition absolute maximum ratings (1) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6.0 pf c i/o i/o capacitance v out = 0v 3.5 8.0 pf pin names description xax data register a inputs data register b outputs xbx data register b inputs data register a outputs xclkab, xclkba clock pulse inputs xsab, xsba output data source select inputs xdir, x oe output enable inputs inputs data i/o (1) operation or function x oe oe xdir xclkab xclkba xsab xsba xax xbx h h x x h or l - h or l - x x x x input input isolation store a and b data l l l l x x x h or l x x l h output input real time b data to a bus stored b data to a bus l l h h x h or l x x l h x x input output real time a data to b bus stored a data to b bus symbol description max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7.0 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 v t stg storage temperature C65 to +150 c i out dc output current C60 to +120 ma 2540 tbl 04 notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all device terminals except fct162xxxt output and i/o terminals. 3. output and i/o terminals for fct162xxxt.
5.13 4 idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges bus a bus b x dir x oe x clkab x clkba x sab x sba h l x xl x 2540 drw 06 transfer stored data to a and/or b note: 1. cannot transfer data to a bus and b bus simultaneously. bus a bus b x dir x oe x clkab x clkba x sab x sba llx x xh x x lx x hl - xx - - - x 2540 drw 07 real-time transfer bus b to a real-time transfer bus a to b storage from a and/or b bus a bus b x dir x oe x clkab x clkba x sab x sba ll x x x l 2540 drw 05 bus a bus b x dir x oe x clkab x clkba x sab x sba ll x x h or l h 2540 drw 08 (1) h l h or l x h x
idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges 5.13 5 dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40 c to +85 c, v cc = 5.0v 10%; military: t a = C55 c to +125 c, v cc = 5.0v 10% 2540 lnk 06 2540 lnk 07 symbol parameter test conditions (1) min. typ. (2) max. unit i odl output low current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) 60 115 200 ma i odh output high current v cc = 5v, v in = v ih or v il, v out = 1.5v (3) C60 C115 C200 ma v oh output high voltage v cc = min. v in = v ih or v il i oh = C16ma mil. i oh = C24ma com'l. 2.4 3.3 v v ol output low voltage v cc = min. v in = v ih or v il i ol = 16ma mil. i ol = 24ma com'l. 0.3 0.55 v notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25 c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. duration of the condition can not exceed one second. 5. the test limit for this parameter is 5 m a at t a = C55 c. symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i i h input high current (input pins) (5) v cc = max. v i = v cc 1 m a input high current (i/o pins) (5) 1 i i l input low current (input pins) (5) v i = gnd 1 input low current (i/o pins) (5) 1 i ozh high impedance output current v cc = max. v o = 2.7v 1 m a i ozl (3-state output pins) (5) v o = 0.5v 1 v ik clamp diode voltage v cc = min., i in = C18ma C 0.7 C 1.2 v i os short circuit current v cc = max., v o = gnd (3) C80 C 140 C 225 ma v h input hysteresis 100 mv i ccl i cch i ccz quiescent power supply current v cc = max., v in = gnd or v cc 5 500 m a 2540 lnk 05 symbol parameter test conditions (1) min. typ. (2) max. unit i o output drive current v cc = max., v o = 2.5v (3) C50 C 180 ma v oh output high voltage v cc = min. i oh = C3ma 2.5 3.5 v v in = v ih or v il i oh = C12ma mil. i oh = C15ma com'l. 2.4 3.5 v i oh = C24ma mil. i oh = C32ma com'l. (4) 2.0 3.0 v v ol output low voltage v cc = min. v in = v ih or v il i ol = 48ma mil. i ol = 64ma com'l. 0.2 0.55 v i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v 1 m a output drive characteristics for fct16646t output drive characteristics for fct162646t
5.13 6 idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges power supply characteristics 2540 tbl 08 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp n cp /2 + f i n i ) i cc = quiescent current (i ccl , i cch and i ccz ) d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at f i symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 1.5 ma i ccd dynamic power supply current (4) v cc = max. outputs open xdir = x oe = gnd one input toggling 50% duty cycle v in = v cc v in = gnd 75 120 m a/ mhz i c total power supply current (6) v cc = max. outputs open f cp = 10mhz (xclkba) 50% duty cycle v in = v cc v in = gnd 0.8 1.7 ma xdir = x oe = gnd one bit toggling fi = 5mhz 50% duty cycle v in = 3.4v v in = gnd 1.3 3.2 v cc = max. outputs open f cp = 10mhz (xclkba) 50% duty cycle v in = v cc v in = gnd 3.8 6.5 (5) xdir = x oe = gnd sixteen bits toggling fi = 2.5mhz 50% duty cycle v in = 3.4v v in = gnd 8.3 20.0 (5)
idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges 5.13 7 switching characteristics over operating range 2540 tbl 09 2540 tbl10 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. 4. this limit is guaranteed but not tested. fct16646t/162646t fct16646at/162646at com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay bus to bus c l = 50pf r l = 500 w 2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns t pzh t pzl output enable time xdir or x oe to bus 2.0 14.0 2.0 15.0 2.0 9.8 2.0 10.5 ns t phz t plz output disable time xdir or x oe to bus 2.0 9.0 2.0 11.0 2.0 6.3 2.0 7.7 ns t plh t phl propagation delay clock to bus 2.0 9.0 2.0 10.0 2.0 6.3 2.0 7.0 ns t plh t phl propagation delay xsba or xsab to bus 2.0 11.0 2.0 12.0 2.0 7.7 2.0 8.4 ns t su set-up time high or low bus to clock 4.0 4.5 2.0 2.0 ns t h hold time high or low bus to clock 2.0 2.0 1.5 1.5 ns t w clock pulse width high or low 6.0 6.0 5.0 5.0 ns t sk (o) output skew (3) 0.5 0.5 0.5 0.5 ns fct16646ct/162646ct fct16646et/162646et com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay bus to bus c l = 50pf r l = 500 w 1.5 5.4 1.5 6.0 1.5 3.8 ns t pzh t pzl output enable time xdir or x oe to bus 1.5 7.8 1.5 8.9 1.5 4.8 ns t phz t plz output disable time xdir or x oe to bus 1.5 6.3 1.5 7.7 1.5 4.0 ns t plh t phl propagation delay clock to bus 1.5 5.7 1.5 6.3 1.5 3.8 ns t plh t phl propagation delay xsba or xsab to bus 1.5 6.2 1.5 7.0 1.5 4.2 ns t su set-up time high or low bus to clock 2.0 2.0 2.0 ns t h hold time high or low bus to clock 1.5 1.5 0.0 ns t w clock pulse width high or low 5.0 5.0 3.0 (4) ns t sk (o) output skew (3) 0.5 0.5 0.5 ns
5.13 8 idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges test circuits and waveforms test circuits for all outputs enable and disable times propagation delay set-up, hold and release times pulse width switch position pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. test switch disable low enable low closed all other tests open open drain 2556 lnk 10 notes: 1. diagram shown for input control enable-low and input control disable-high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns 2556 drw 09 2556 drw 07 2556 drw 05 2556 drw 06 2556 drw 08 definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
idt54/74fct16646t/at/ct/et, 162646t/at/ct/et fast cmos 16-bit bus transceiver/register military and commercial temperature ranges 5.13 9 ordering information idt xx fct xxxx device type x package x process blank b pv pa pf e 16646t 16646at 16646ct 16646et 162646t 162646at 162646ct 162646et commercial mil-std-883, class b shrink small outline package (so56-1) thin shrink small outline package (so56-2) thin very small outline package (so56-3) cerpack (e56-1) non-inverting 16-bit transceiver/register temperature range 54 74 C55 c to +125 c C40 c to +85 c 2540 drw 14
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